Ling adder

In electronics, a Ling adder is a particularly fast binary adder designed using H. Ling's equations and generally implemented in BiCMOS. Samuel Naffziger of Hewlett Packard presented an innovative 64 bit adder in 0.5 μm CMOS based on Ling's equations at ISSCC 1996. The Naffziger adder's delay was less than 1 nanosecond, or 7 FO4. See Naffziger's paper below for more details.

Equations

4-bit Ling adder, Sklansky architecture:

gm1=0
pm1=0
p0 = a0 OR  b0    
g0 = a0 AND b0    
d0 = a0 XOR b0    
p1 = a1 OR  b1
g1 = a1 AND b1
d1 = a1 XOR b1
p2 = a2 OR  b2
g2 = a2 AND b2
d2 = a2 XOR b2
p3 = a3 OR  b3
g3 = a3 AND b3
d3 = a3 XOR b3
'Level1----------------Distance=2^0=1
'(G,P) = (g,p) o (g,p)=(g,p)
'GLi = gi OR gi-1
'PLi = pi AND pi-1    'Distance=1
GLm1 = 0              'for k<0
PLm2 = 0              'for k<0
'(GL0,PLm1)
GL0 = g0 OR  gm1
PLm1=0                'for k<0
'(GL1,PL0)
GL1 = g1 OR  g0
PL0 = p0 AND pm1      'Distance=1
'(GL3,PL2)
GL3 = g3 OR  g2
PL2 = p2 AND p1       'Distance=1
'Level2---------------------------Distance=2^1=2
'(G,P) = (g,p) o (g',p') = (g OR (p AND g'),p AND p')
'G=g OR (p AND p')
'P=      p AND p'
'(GL2,PL1) o (GL1,PLm1)          '
GL21 =  g2 OR p1 AND GL1         '
'(GL3,PL2) o (GL1,PL0)           '
GL31 = GL3 OR PL2 AND GL1        '
'Ling PsevdoCarry (H)-------------------
Hm1 = GLm1                   'Ling PsevdoCarry
H0  = g0                     'Ling PsevdoCarry
H1  = GL1                    'Ling PsevdoCarry
H2  = GL21                   'Ling PsevdoCarry
H3  = GL31                   'Ling PsevdoCarry
'SUM-------------------------------------------------
'si=(/Hi-1 AND di) OR (Hi-1 AND (di XOR pi-1))
s0 = (1-Hm1) AND d0 OR Hm1 AND (d0 XOR pm1)  's0=d0
s1 = (1-H0 ) AND d1 OR H0  AND (d1 XOR p0 )
s2 = (1-H1 ) AND d2 OR H1  AND (d2 XOR p1 )
s3 = (1-H2 ) AND d3 OR H2  AND (d3 XOR p2 )
s4 = p3 AND H3  'Cout=s4
  1. H. Ling, "High Speed Binary Parallel Adder", IEEE Transactions on Electronic Computers, EC-15, p. 799-809, October, 1966.
  2. H. Ling, "High-Speed Binary Adder", IBM J. Res. Dev., vol.25, p. 156-66, 1981.
  3. R. W. Doran, "Variants on an Improved Carry Look-Ahead Adder", IEEE Transactions on Computers, Vol.37, No.9, September 1988.
  4. N. T. Quach, M. J. Flynn, "High-Speed Addition in CMOS", IEEE Transactions on Computers, Vol.41, No.12, December, 1992.
  5. S. Naffziger, "A Sub-Nanosecond 0.5um 64b Adder Design", Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, San Francisco, 8-10 Feb. 1996, p. 362 –363.
  6. S. Naffziger, "High Speed Addition Using Ling's Equations and Dynamic CMOS Logic", U.S. Patent No. 5,719,803, Issued: February 17, 1998.
  7. G. Dimitrakopoulos, D. Nikolos, "High-Speed Parallel-Prefix VLSI Ling Adders", IEEE Transaction on Computers, Vol.54, No.2, February, 2005.


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